6502 CPU
Hardware theme
A simplified/cost reduced clone of the Motorola 6800 designed by the designers of the 6800. It enjoyed some popularly for a few decades.
6
games
4platforms
Games requiring a 65C816/65C802 CPU should not be tagged as 6502 games except in rare cases when a single game has specific features when running on either or running on both (or modes of the 65Cxxx).
Manufacture's original price is $25 USD ($122.22 in 2021 USD). The following article is written with this price in mind. The initial $20 price was promotional and limited; no one ever created a mass-market product using original 6502 chips that were sold for $20.
The original NMOS 6502 has 3,510 transistors.
In 1978, Dann McCreary created the "8080 Simulator for the 6502" for emulating an 8080 CPU on a KIM-1. It was later ported to Apple II.
The following article begins with in depth information about the original 6501 & 6502 (NMOS). Discussion of the 65C02 (CMOS) and later variants will follow.
The 6502, in some instances, could fetch the next instruction while executing the current instruction. The Intel 8080 was the first chip that could do this with the 6502 close behind. MOS and Intel each arrived at this feature independently. The 8008 was priced 34.32 times more than the 6502.
Team 6502:
Chuck Peddle
John Paivinen
Bill Mensch
Will Mathis
Rod Orgill
Ray Hirt
Harry Bawcum
Mike James
Terry Holt
Team 6502 aimed to replace, outperform, and undersell the 6800. Chuck Peddle was very vocal on these points. When the 6501 and 6502 were announced, many thought is was a scam because no one could make a CPU that sold so cheaply. When Intel and Motorola responded by dropping their prices, other people started to believe.
Warning, <politics>
The 6502 was first and foremost a product to fill a need in the market that no other CPU was providing. It was what customers were asking for and the industry was refusing to provide. However, it became an every man's CPU and forced all CPU manufacturers to reduce their prices. This lead to products with CPUs in them to become available to people from all economic classes. It was inevitable that CPUs would become ubiquitous. But it was the 6502 that holds the credit for starting it all. It didn't do this by offering a substandard product, it did it by offering a better one.</politics>
A Condensed History:
*First-hand accounts of the lawsuit, project progression, organisation of the team, and other details seem to contradict one another on a number of points. I think that there may be a bit of selective memory at play, or just perhaps just fading memories being told the way an audience likes to hear it:) But the technical specs are not disputed.
**projection masking did require physical contact with the projection mask that had similar contamination and defect issues as physical masking on silicon. However, the projection mask was much, much more fault tolerant than a silicon wafer that could be ruined by microscopic defects and damage. MOS was operated much like a small independent company without the same resources as their multi-million dollar competition had. Motorola had Clean Rooms and procedures to minimize risk to a projection mask during manufacture. To bad they weren't using them for projection masking yet. MOS had a spare room and a competent janitor. The projection mask was placed on a very large table and engineers, mostly Bill Mensch, wore clean clothes and socks without holes while they hand crafted the projection mask. Clean socks without holes where especially important because the engineers had to carefully climb on top of the mask to complete the carving. If a toenail scratched the mask, it would produce defective chips. Remember, Mensch only made one mistake on the first batch. 5 years later, MOS would begin construction on a Clean Room but the project ran out of funds before completion. All MOS chips are hand-crafted and not toe-crafted.
***An 8-bit stack is not that bad. As late as 2017, new chip designs were being manufactured that used 6-bit stacks. Apple, Atari, Commodore, Acorn, BBC, Ohio Scientific, Oric, Nintendo, and NEC did quite well offering many systems with 8-bit stacks in their CPUs over many years. For comparison, Coleco. Radio Shack, Sinclair, Sharp, Epson, Cambridge, Amstrad, VTech, Texas Instruments, Bandai, Mattel, Memotech, Timex, made systems with 16-bit stacks in their CPUs. (There's some overlap I didn't list, the 65C816 with a 16-bit stack, for example was used in systems by some of companies on my 8-bit list above.)
†When the lawsuit was settled it left some 3rd parties in a quandary about exactly who owned what concerning the 6501. Many of the patents named in the suit also applied to the 6502. Motorola had listed 25 patents in their suit against the 6501. None were dismissed before the settlement. No ruling was made as to which, if any, of Motorola's patents applied to the 6501 or 6502. It has been speculated that when companies made their own versions of the 6502 that changes were made, in-part, to avoid violating Motorola patents.
‡Some members of team 6502 held patents on design aspects of the 6800. Mensch co-holds the patent of the 6800 CPU itself, the 6820/21 PIA patent, 6850 ACIA patent, and 6860 modem chip patent. He also co-holds the 6502's Decimal Correct Circuitry patent (the feature left out of the NES' Ricoh 2A03 6502 clone)
◊Difficult, but not impossible. First, there are various ways the 6502's two clock outputs can be modified for use with external components. Also important, the 6502 can be made to accept an external signal to modify the internal clock, with limitations. The external clock does not override the internal one. It gets complicated. Some of the 6502 components use combinational logic (clockless logic). Many CPUs may have a bit of combinational logic going on but the 6502 has quite a bit more than most. The 6502's clock is also two-phase and can (should) be synchronized twice per machine cycle. This is how/why the 6502 can fetch the next instruction while processing the current one. This synchronizing function allows for iterations with a clock speed that is slower that the internal clock. This is helpful if the 6502 needs to interact with slower comments, such as an EEPROM during boot. 500KHz is apparently MOS' official minimum spec. Bugs begin occurring under 100kHz because the registers can lose their state. 50KHz has been achieved in real world use. Some features of the 6502 are not available when using a different clock speed.
◊◊Since the suit was filed between the dates of official public sale of the 6501 and 6502, the rumor that the 6502 was a response to the suit must seem plausible topeople who are unaware of the complications of designing and manufacturing a new CPU in 1975. Scratch that; people who are unaware of the complications of designing and manufacturing a new CPU. They didn't have FPGA and the cloud back then, which can get someone's new CPU design into hardware in about 48 hours. But even with that, the time for the design phase and write to hardware, today, would barely allow for a new CPU in under 30 days.
◊◊◊MOS was shocked to discover, at Wescon, that no one was actually allowed to sell anything at Wescon. Being only momentarily deterred, they rented an addition hotel room to sell out of. Visitors to the MOS booth were given directions to walk to the sales room. In your face, Wescon.
The 8502 is an HMOS-II version of the 6502. It used less power, produced less heat, and was physically smaller. Being smaller, it was cheaper (read A Condensed History above to better understand why).
[wip]
MOS 4510
MELPS M50740 (600 variants are not all listed)
Ricoh 5A22
MOS 6501 A, 6501 B, 6501 C
MOS 6502 A, 6502 B, 6502 C
MOS 6503
MOS 6504
MOS 6505
MOS 6507
MOS 6508
MOS 6509
MOS 6510, 6510T
MOS 6512
MOS 6513
MOS 6514
MOS 6515
? 65802
? 65816
WDC 65C02
WDC 65C134
WDC 65C265
WDC 65C802
WDC 65C816
MOS 65CE02
MOS 7501
MOS 8500
MOS 8501
MOS 8502
Hudson Soft HuC6280
Nintendo SA-1 (65C816 based)
Ricoh RP2A03
Ricoh RP2A07
Manufacture's original price is $25 USD ($122.22 in 2021 USD). The following article is written with this price in mind. The initial $20 price was promotional and limited; no one ever created a mass-market product using original 6502 chips that were sold for $20.
The original NMOS 6502 has 3,510 transistors.
In 1978, Dann McCreary created the "8080 Simulator for the 6502" for emulating an 8080 CPU on a KIM-1. It was later ported to Apple II.
ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA
The following article begins with in depth information about the original 6501 & 6502 (NMOS). Discussion of the 65C02 (CMOS) and later variants will follow.
The 6502, in some instances, could fetch the next instruction while executing the current instruction. The Intel 8080 was the first chip that could do this with the 6502 close behind. MOS and Intel each arrived at this feature independently. The 8008 was priced 34.32 times more than the 6502.
Rotate Right (ROR) can be performed on a memory address or the accumulator. But the very first batch of 6501 and 6502 chips would perform an ASL instead. Only chips manufactured in 1975 have this 'bug'. Some KIM-1 computers have the ROR 'bug'. Note: ROR exists in the 6501 and first revision 6502 as an unimplimented opcode (that doesn't do an ROR). There are lots of those in the 6502 and no one calls those bugs. According to both Chuck Peddle and Bill Mensch, the decision was intentionally made to not have an ROR instruction because it was considered an unnecessary feature by Chuck Peddle. There were 189 of those, and no one calls those bugs. But many computer designers, especially amatures, felt that and ROR was necessary, especially in a chip with an ROL. Remember back to school, if you happened to have taken such a class, there was an assignment to design an algorithm for a robot to solve a maze. The robot could only turn right, not left. Implementing a left turn would only occasionally save two turns and not make a tremendous increase in the robot's performance. Yet many students wanted a left turn. If told a buggy left turn existed, some students would have attempted to use it anyhow, causing the robot to fail and then blamed the 'bug' for the failure. Similar logic supports the reasons ROR was left out then later added to the 6502 design. Skeptics may claim that a real bug is being explained away, but physical evidence supports that the ROR instruction was initially included in the design and intentionally removed before the final design. The path of wires from the ROR instruction to the internal transitors of the chip are there but unconnected. For this to be a bug, this line would have to be connected to a great many transistors to show an effort was made to include ROR. The require data control line and at least 30 transistors to implement ROR don't exist in the 1st revision, only in later chip revisions.
Memory Indirect Jump (JMP) has a bug. Jumping to any address ending in FF will cause a jump to the next location as well. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Indexed reads that cross page boundaries will read an invalid address before reading the correct one. This adds a clock cycle to instructions that usually take less. Annoying but mostly harmless and can be worked around, unless there is hardware attached to the system that is triggered by reads (Such as I/O handshaking and resetting an IRQ timer). The first read returns garbage so in addition to confusing the hardware, that hardware may also react to the unpredictable value. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Similar to the extra read bug, there is an extra write bug for all opcodes that are read-modify-write. Like the extra read bug, the first write is invalid. Unlike the extra read bug, it is predictable. The data of first write is equal to the data of the read and the extra clock cycle always happens because the extra write always happens. Also similar, some hardware gets confused. Simple fix, don't read-modify-write hardware resisters directly. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Binary-coded decimal quirk (BCD quirk). It is normal and proper for a CPU in binary-coded decimal mode to revert to binary mode when a hardware interrupt occurs. The 6502 does not. Fortunately, this issues can easily be worked around in the Kernal (ROM) for the system. The Kernal should disable or re-direct hardware IRQ that tries to interrupt while BCD math is being performed. Unfortunately, the Commodore 64 Kernal did not. It is up to developers to manually protect BCD math operations. All NMOS 65xx chips have this quirk but CMOS and HMOS variants do not.
Failed BRK. The BRK operation stops the current software from running. The was intended to be used for software debugging. Typically, the debug version would end a reaction to errors with a BRK command so the programmer could examine the state of the system in a machine language monitor to determine the cause of the error. Or more crudely, inserted in a specific spot in misbehaving software in an attempt to locate and define unintended behavior (this 2nd arduous task may be required because of the quirk soon to be described). But it became typical practice to abuse the BRK by using it in a process of routing program execution using a simple jump table (The 6800 had a software interrupt instruction to do all this properly. Developers were creatively implementing an artificial SWI. The BRK instruction is technically a type of SWI). This often was also part of software debugging, and useful to automatically tell the developer specific information about what went wrong, but sometimes developers actually included this hack in final software for purposes other than debugging (or forgot to remove it, or didn't bother to remove it, or expected end users to use it to report bugs). Remember how the 6502 can fetch the next instruction while executing the current one? If a hardware IRQ occurs at this moment, it will replace the BRK operation (no BRK occurs). This can sabotage a developer's debugging routines. The program can stop at a secondary error caused indirectly by the primary error, obscuring the primary error. Or worse, the program continues executing improperly and does not indicate any error that could cause the unintended behavior. Even worse, is when the BRK jump table is purposefully left into a released version, the developer does not know that hardware IRQ is stopping BRK, and end users are encountering unintended behavior that the developer never encountered. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
RTS Trick. JSR & RTS use the Stack instead of a fixed RAM location. JSR & RTS are used to jump to and return from subroutines like any other CPU. But, other CPUs jump to and return from specified memory locations. 65xx CPUs use JSR to add the memory location of the next instruction into the Stack before going to the subroutine. When RTS tells the software to return, it returns to the Stack where the memory location of the next instruction is removed from the Stack while the program counter changes to that value. This little bit of reentrant behavior adds 1 cycle per subroutine call compared to an indirect jump, but saves up to 4 bytes of RAM per subroutine used in the code. That's not the trick. Where this gets really interesting is when it is used to replace a jump table with long chains of branching code. Instead, the developer can write a simple return address table to the Stack. That's the RTS Trick. All 65xx CPUs and variants and derivatives of variants do this.
The 65xx design has space for 256 opcodes. MOS only used 151. The 105 undocumented opcodes are duplicates, buggy duplicates, do nothing, run multiple operations correctly, run multiple operations incorrectly, simply crash the hardware, and/or trigger a race condition (HCF) in some 65xx versions. When manufacturing 65xx chips, these undocumented opcodes can be used to created new documented opcodes, if the manufacturer needs them. Some hardware traps the opcodes so that all undocumented opcodes are BRK (stop the current software). So, if a developer does use undocumented opcodes on an unrestricted 6502 system, the software probably won't not work in a system that traps these opcodes. Undocumented opcodes were sometimes used for DRM/copy protection, and legitimate buyers could not run their software on certain hardware revisions of otherwise compatible systems because the software depended on having or not having the BRK occurring. The 65C02 replaces all undocumented opcodes with NOP (no operation), for similar end results. But, manufactures can still replace the extra NOP instructions with their own. All variants of the 65802 and 65816 by Western Design Center leave no opcodes unused. Meaning manufactures would break compatibility if they changed any, even if the 65xxx is running in 65xx mode. All NMOS 65xx chips have undocumented opcodes but CMOS and HMOS variants might not.
N, V, and Z Flags only work correctly in binary mode. When the 6502 is doing BCD math, the N, V, and Z Flags generally do not do anything useful (but are fully predictable). This quirk is widely considered an efficient way for software to determine if it is running on and NMOS CPU since All NMOS 65xx chips have this quirk but CMOS and HMOS variants do not.
MOS only manufactured one "6502" but they sold 3 variants. How could/why would, they possible manufacture only 1 variant and end up with 3 variants to sell? Well, each chip had to be diagnosed to verify it had been burned correctly (read A Condensed History to better understand why) and ran without error using an external clock at 4MHz. When chips ran with errors, they'd turn the clock down to 2MHz and check it again, then 1MHz and check again. Errorless 4MHz chips were stamped "6502 C". Errorless 2MHz, "6502 B". And errorless 1MHz chips, "6502 A". Failing all three tests was grounds to be recycled. After being stamped, each chip would undergo more rigorous quality assurance.
Memory Indirect Jump (JMP) has a bug. Jumping to any address ending in FF will cause a jump to the next location as well. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Indexed reads that cross page boundaries will read an invalid address before reading the correct one. This adds a clock cycle to instructions that usually take less. Annoying but mostly harmless and can be worked around, unless there is hardware attached to the system that is triggered by reads (Such as I/O handshaking and resetting an IRQ timer). The first read returns garbage so in addition to confusing the hardware, that hardware may also react to the unpredictable value. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Similar to the extra read bug, there is an extra write bug for all opcodes that are read-modify-write. Like the extra read bug, the first write is invalid. Unlike the extra read bug, it is predictable. The data of first write is equal to the data of the read and the extra clock cycle always happens because the extra write always happens. Also similar, some hardware gets confused. Simple fix, don't read-modify-write hardware resisters directly. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
Binary-coded decimal quirk (BCD quirk). It is normal and proper for a CPU in binary-coded decimal mode to revert to binary mode when a hardware interrupt occurs. The 6502 does not. Fortunately, this issues can easily be worked around in the Kernal (ROM) for the system. The Kernal should disable or re-direct hardware IRQ that tries to interrupt while BCD math is being performed. Unfortunately, the Commodore 64 Kernal did not. It is up to developers to manually protect BCD math operations. All NMOS 65xx chips have this quirk but CMOS and HMOS variants do not.
Failed BRK. The BRK operation stops the current software from running. The was intended to be used for software debugging. Typically, the debug version would end a reaction to errors with a BRK command so the programmer could examine the state of the system in a machine language monitor to determine the cause of the error. Or more crudely, inserted in a specific spot in misbehaving software in an attempt to locate and define unintended behavior (this 2nd arduous task may be required because of the quirk soon to be described). But it became typical practice to abuse the BRK by using it in a process of routing program execution using a simple jump table (The 6800 had a software interrupt instruction to do all this properly. Developers were creatively implementing an artificial SWI. The BRK instruction is technically a type of SWI). This often was also part of software debugging, and useful to automatically tell the developer specific information about what went wrong, but sometimes developers actually included this hack in final software for purposes other than debugging (or forgot to remove it, or didn't bother to remove it, or expected end users to use it to report bugs). Remember how the 6502 can fetch the next instruction while executing the current one? If a hardware IRQ occurs at this moment, it will replace the BRK operation (no BRK occurs). This can sabotage a developer's debugging routines. The program can stop at a secondary error caused indirectly by the primary error, obscuring the primary error. Or worse, the program continues executing improperly and does not indicate any error that could cause the unintended behavior. Even worse, is when the BRK jump table is purposefully left into a released version, the developer does not know that hardware IRQ is stopping BRK, and end users are encountering unintended behavior that the developer never encountered. All NMOS 65xx chips have this bug but CMOS and HMOS variants do not.
RTS Trick. JSR & RTS use the Stack instead of a fixed RAM location. JSR & RTS are used to jump to and return from subroutines like any other CPU. But, other CPUs jump to and return from specified memory locations. 65xx CPUs use JSR to add the memory location of the next instruction into the Stack before going to the subroutine. When RTS tells the software to return, it returns to the Stack where the memory location of the next instruction is removed from the Stack while the program counter changes to that value. This little bit of reentrant behavior adds 1 cycle per subroutine call compared to an indirect jump, but saves up to 4 bytes of RAM per subroutine used in the code. That's not the trick. Where this gets really interesting is when it is used to replace a jump table with long chains of branching code. Instead, the developer can write a simple return address table to the Stack. That's the RTS Trick. All 65xx CPUs and variants and derivatives of variants do this.
The 65xx design has space for 256 opcodes. MOS only used 151. The 105 undocumented opcodes are duplicates, buggy duplicates, do nothing, run multiple operations correctly, run multiple operations incorrectly, simply crash the hardware, and/or trigger a race condition (HCF) in some 65xx versions. When manufacturing 65xx chips, these undocumented opcodes can be used to created new documented opcodes, if the manufacturer needs them. Some hardware traps the opcodes so that all undocumented opcodes are BRK (stop the current software). So, if a developer does use undocumented opcodes on an unrestricted 6502 system, the software probably won't not work in a system that traps these opcodes. Undocumented opcodes were sometimes used for DRM/copy protection, and legitimate buyers could not run their software on certain hardware revisions of otherwise compatible systems because the software depended on having or not having the BRK occurring. The 65C02 replaces all undocumented opcodes with NOP (no operation), for similar end results. But, manufactures can still replace the extra NOP instructions with their own. All variants of the 65802 and 65816 by Western Design Center leave no opcodes unused. Meaning manufactures would break compatibility if they changed any, even if the 65xxx is running in 65xx mode. All NMOS 65xx chips have undocumented opcodes but CMOS and HMOS variants might not.
N, V, and Z Flags only work correctly in binary mode. When the 6502 is doing BCD math, the N, V, and Z Flags generally do not do anything useful (but are fully predictable). This quirk is widely considered an efficient way for software to determine if it is running on and NMOS CPU since All NMOS 65xx chips have this quirk but CMOS and HMOS variants do not.
MOS only manufactured one "6502" but they sold 3 variants. How could/why would, they possible manufacture only 1 variant and end up with 3 variants to sell? Well, each chip had to be diagnosed to verify it had been burned correctly (read A Condensed History to better understand why) and ran without error using an external clock at 4MHz. When chips ran with errors, they'd turn the clock down to 2MHz and check it again, then 1MHz and check again. Errorless 4MHz chips were stamped "6502 C". Errorless 2MHz, "6502 B". And errorless 1MHz chips, "6502 A". Failing all three tests was grounds to be recycled. After being stamped, each chip would undergo more rigorous quality assurance.
Team 6502:
Chuck Peddle
John Paivinen
Bill Mensch
Will Mathis
Rod Orgill
Ray Hirt
Harry Bawcum
Mike James
Terry Holt
Team 6502 aimed to replace, outperform, and undersell the 6800. Chuck Peddle was very vocal on these points. When the 6501 and 6502 were announced, many thought is was a scam because no one could make a CPU that sold so cheaply. When Intel and Motorola responded by dropping their prices, other people started to believe.
Warning, <politics>
The 6502 was first and foremost a product to fill a need in the market that no other CPU was providing. It was what customers were asking for and the industry was refusing to provide. However, it became an every man's CPU and forced all CPU manufacturers to reduce their prices. This lead to products with CPUs in them to become available to people from all economic classes. It was inevitable that CPUs would become ubiquitous. But it was the 6502 that holds the credit for starting it all. It didn't do this by offering a substandard product, it did it by offering a better one.</politics>
A Condensed History:
MOS Technology changed owners and names several times:
Rockwell Automation owned the Allen-Bradley brand
1969 Allen-Bradley created MOS Technology
1975 MOS Technology was purchased by its employees when it got sued by Motorola
(1976 Bill Mensch left MOS to form the independent company, Western Design Center)
1976 Commodore bought MOS and renamed it Commodore Semiconductor Group (Commodore made calculators at the time. CSG continued to use the MOS logos and brand name)
1994 GMT Microelectronics merges with GSG when MOS employees buy it from a bankrupt Commodore
2001 due to environmental pollution left by Commodore, GMT abandons all MOS assets and the the company becomes defunct
2001 onward, Western Design Center continues to manufacture and improve 65xx technology
Technically, Allen-Bradley was the original owner of the 6501 and 6502. Multiple patents owned by multiple entities are used by the 65xx architecture so currently no one entity could rightfully be called the 'owner'. In practice, Western Design Center has rights to everything 65xx and is the effective owner. Other manufactures can create 6502 clones using alternate features to avoid patent infringement. For full 65xx compatibility, consulting with Western Design Center is the place to start
Rockwell Automation owned the Allen-Bradley brand
1969 Allen-Bradley created MOS Technology
1975 MOS Technology was purchased by its employees when it got sued by Motorola
(1976 Bill Mensch left MOS to form the independent company, Western Design Center)
1976 Commodore bought MOS and renamed it Commodore Semiconductor Group (Commodore made calculators at the time. CSG continued to use the MOS logos and brand name)
1994 GMT Microelectronics merges with GSG when MOS employees buy it from a bankrupt Commodore
2001 due to environmental pollution left by Commodore, GMT abandons all MOS assets and the the company becomes defunct
2001 onward, Western Design Center continues to manufacture and improve 65xx technology
Technically, Allen-Bradley was the original owner of the 6501 and 6502. Multiple patents owned by multiple entities are used by the 65xx architecture so currently no one entity could rightfully be called the 'owner'. In practice, Western Design Center has rights to everything 65xx and is the effective owner. Other manufactures can create 6502 clones using alternate features to avoid patent infringement. For full 65xx compatibility, consulting with Western Design Center is the place to start
While Chuck Peddle was working at Motorola on the 6800 and its support chips, he noted that most of the 6800's instruction set and features were not being used very much in the wild. A version of the 6800 with fewer instructions, less cost, and smaller size was indirectly being requested by engineers who were compiling lists of required instructions that were much smaller than "all these fancy instructions". A streamlined 6800 would solve some of the major problems that were overwhelming Motorola time (and also, most semiconductor companies). A reduced instruction set allowed for a smaller chip. Having a smaller chip in the end product was not that big of a deal. It mattered during manufacture, because multiple copies of chips were printed on a single silicon wafer and then it was divided into individual chips. A smaller chip on the wafer meant more chips per wafer. This was a major cost savings of the idea. Silicon wafers were not just high in cost, they were high in demand and semiconductor companies were all experiencing shortages at the time. A company might be willing to pay an outrageous amount for the silicon, but it didn't matter because there wasn't enough silicon for them to buy. More chips on a wafer was cheaper and increased the production rate by using less of the wafer per chip. Then there is the issue of defects. Invariably, when chips are printed to silicon wafers there are microscopic defects. These can cause a chip to fail. The smaller a chip, the less chance of a defect occurring on it. So, smaller chips mean scrapping less defective chips per wafer. Key management at Motorola's semiconductor division at the time did not see things that way. They considered Peddle's project to be one more problem that needed to be eliminated before conception. Motorola ordered Peddle to stop working on it. Peddle informed Motorola that he would be claiming intellectual property rights of the project. This would eventually lead to Motorola firing the semiconductor management team and a public admittance by the CEO of Motorola that they had missed an opportunity. Chuck Peddle offered the idea to John Paivinen, a founder of MOS technology, who had formally worked on the 6800 with Peddle. Paivinen "immediately got it". MOS Technology was struggling at the time, having invested in development of a line of custom calculator chips only to have their customer back out of the deal. A streamlined 6800 seemed to be a safe bet to keep the company solvent but really it was expected to do great in the marketplace. Peddle persuaded 6 other 6800 team members to join him at MOS. Another employee from the Motorola 6800 team joined later. Peddle warned all of these partners-in-scheme not to possess any of Motorola's documents. There was no need of them, the team had all the important pieces of knowledge stored in their heads. It was later concluded that Mike James managed to do something problematic for MOS regarding this order.
There were further optimizations to be made besides reducing instructions. Most CPUs at the time, and the 6800, needed to be supplied with -5, +5, and +12 volts available at all times. There were pins for all of these and these pins had to be routed to internal components of the IC (taking up more space). The routing from pins to internal logic components is many, many times larger than the internal logic components on any CPU. Peddle and his team created a depletion-load nMOS (Not entirely HMOS, HMOS came much later) design that used an internal voltage doubler to so that just a 5 volt pin and ground pin could supply the chip with all power needs. (The 6502 has two ground pins, the 2nd is not connected directly to logic components?). This reduced complexity of the CPU, support chip interface, and power supply of the entire end product (this saved money for MOS and MOS' customers). And yet again, smaller, cheaper.
Every CPU needs a clock signal for itself and certain support components (such as RAM) and as this signal travels over wires, it dissipates (checkout an original-run Apple /// to see the results of failing to compensate for clock signal dissipation. Motherboards can compensate for this with an ultra strong signal from a single source with internal clock divider(s) or very nearby external divider(s) centrally located to be near all the components that require precision timing (certain sound and video components, for example, can get away with being located relatively far from the CPU and even use a separate clock). Peddle and his team design an internal clock. Less complexity, less components, less pins, smaller, cheaper; this saved money for MOS and MOS' customers, yet again. Note however, this makes it difficult to change clock speed in manufactured chip◊ (this turned out to be worth the trade for most customers).
There's more. The 6800 used a three state bus. This allowed a 6800 to be used as or with co-processors of arbitrary architecture (Z80, 808x, 680x0, Z-8000, etc) and also allow direct memory access (DMA) with any peripheral while co-processing. Hobbyists and even a few developers actually did such things on occasion, but this was not needed in most practical real-world applications. These customers would just have to develop an external system to manage memory and coordinate co-processing; which is what they usually did anyhow, even when using a 6800. Peddle suggested a single 74158 could be used to implement what the 6800 did with its 3-state bus. So, guess what? This made the chip simpler, smaller, cheaper. This simplification saved money for MOS and MOS' customers. Even when customers added hardware to implement DMA and co-processing, it was cheaper than using a 6800. Some say the removal of the 3-state bus was the most significant factor in size reduction.
Still more. The 6800 had two general purpose 16-bit registers. Very convenient for programming but each register had to physically connect to all of the decoders for each instruction (more circuitry taking up space). The stack register was a convenient 16-bits in size (8080 and z80 used a 16-bit stack as well). But again, this took up way to much space. Peddle's design would use a single general purpose register and 8-bit stack***. Removing the '2nd register' also meant removing all the instructions that dealt with comparing, relating, and transferring values between the two registers. You know what that means... Yup, simpler, smaller, cheaper. Where the general register had been in the 6800, the 6502 two non-general 8-bit X and Y registers. Many tasks are just terrible to code with only one general register to use so there is a workaround provided by MOS. The 6502 is designed so it can use the first 256 bytes of RAM as registers. To put it another way, The 6502 can use the entire zero page of RAM as registers. Because of the physics of sending receiving a signal to external RAM and the time it takes for capacitors to charge and discharge bits in RAM, these 'external' registers can be very slow to read and write compared to internal registers, in modern systems. But back in the 1970s, many CPUs were actually slower than RAM. Even if a system designed around a 6502 used slower/cheaper RAM, the zero page was best to be made of RAM as fast as the 6502 could address it. RAM that was as fast as the 6502 on the zero page was not overly detrimental compared to the international register. By design, using the zero page took three cycles but addressing higher memory took 4 or more.
Example code:
LDA $EI ; copying only 1 byte of data from memory to accumulator, zero page, 3 cycles
LDA $EIEI ; copying 2 bytes of data from memory to accumulator, above zero page, 4 cycles
Example code:
LDA $EI ; copying only 1 byte of data from memory to accumulator, zero page, 3 cycles
LDA $EIEI ; copying 2 bytes of data from memory to accumulator, above zero page, 4 cycles
After unused instructions were eliminated, the team eliminated rarely used instructions as well. That left just a few more instructions to axe. There were some convenient and used functions that could be implemented in simpler ways. The 6800 could use instructions directly to compare numerical values and branch based on the result. But the same could be done by applying certain math instructions to the accumulator (general register) and using the resulting flag changes to conditionally branch. Coding this was more complex but just as fast (or sometimes faster) to execute. This left 56 instructions out of the original 72. Although, the initial batch sold to customers listed 55 instructions in the documentation (sold separately). ROR had a bug and so was left out of the documentation until a fixed version of the chip began manufacture. Note*, this is in direct contradiction to Chuck Peddle's and Bill Herd's insistence that Bill Mensch got the chip right on the first try. However, having only one error and getting it right on the second try is still darned impressive. And, I can't confirm this, but the ROR bug seems to be the only time Bill Mensch made a mistake in a CPU, ever! Ironically, Mensch added his signed initials to the first defective batch and they were removed for subsequent manufacture of the fixed chip.
Then there was the final cost savings measure. Integrated circuit 'negatives' can be created by physically masking silicone wafers to protect areas that are not to be 'burned' with circuitry. The masking is peeled away after the burn. Adding masking is a step that exposes the wafer to dust. Masking can then fail to peel leaving majuscule or minuscule pieces. If a bit of mask after, or dust before or after, is left sitting on an individual chip or the masking apparatus, that chip will be defective. But, if only it were only that bad. All chips burned after a masking defect is introduced would have the new defect. Manually removing dust and leftovers is not an option as doing so itself introduces impurities and microscopically damages surface. For a good batch, 90% of the chips on a wafer could be lost in a single masking step. That 90% of chips destroyed on 1st masking, then 90% of those remaining destroyed on 2 masking, then 90% of those... (90% of 90% of 90% of 90% of 90% of 90% of 90% of 90% of 90% of 90% of 90% of 90% destroyed). Couple this with the aforementioned defects and you'd end up with many wafers of few to no usable chips. The 6800 required 6 steps of masking and unmasking, yah. So, John Paivinen promised Peddle that MOS wouldn't be doing that with his project. Peddle's chip would also required 6 masking steps. But MOS began to shift their entire semiconductor production to projection masking that did not require physical contact with the wafer**. MOS was ready in time for Peddle's team. The fail rate was reduced to a mere 30% of chips (that is, after 6 steps of projection masking, 70% of every chip on every wafer was good. Completely wasted wafers didn't happen).
It is commonly said that MOS was sued for the 6501 and made the 6502 afterwords to avoid further litigation. This is not true◊◊. On September 16, 1975, large jars of 6501 and 6502 chips were offered to the public at the Wescon event◊◊◊. Strictly, neither chip were 'publicly' sold at this time. The 6501 would publicly sold that month. The 6502 was publicly sold in late November◊◊. Buyers took chips from the top of the pile in the jar. The bottom half of the jars were populated with the %30 of defective chips. The jars were an impressive display since other CPU manufactures of the day would have taken 3 to 6 years before having enough newly designed chips to fill a single jar. MOS had done the same thing in about 15 months. The 6501 could be substituted directly where a 6800 would be plugged in. Software for such a 6800 device would likely need to be altered due to the 6501's reduced instruction set and features removal, but hardware would likely remain unchanged or even have supporting hardware removed from the design. Some of the features on Peddle's chip like the internal clock and multi-voltage hardware were not included. The 6501's use was actually rather limited and was perhaps expected to gain just a few customers who had 6800 hardware late in the design phase and could swap in a 6501 with minimal effort to save massive costs. The was little reason to design new hardware around the 6501. Nor was their a compelling advantage to updating an existing hardware design to use the 6501. Where it was extremely useful is for someone to plug it into their 6800 board a play around with it. Hobbyists and Engineers lined up at events to do exactly this. It was definitely expected that the 6501 would lower the cost of 6800 chips. Peddle said often that the 6501 was "an in your face to Motorola." Which is probably on the list of reasons Motorola sued MOS on November 3rd despite the many complications involved‡.
The industry and law at the time did not have the totalitarian systems in place to prevent or even discourage a person or team from leaving a company and creating a replica of their product for a competing company (except maybe at RCA). A company could have employment clauses in place for this purpose but management of the Motorola semiconductor division apparently didn't have a strong system of clauses or didn't know the most effective ways to use them. Peddle and his team had very likely not broken any laws*. And, Motorola had most likely walked right into a trap of their own policies by dismissing Peddle's idea. Trade secrets were pretty much not applied to the inner workings of CPUs at the time (they were available at the library and bookstores) and anybody could have done what Peddle did. The fact that Peddle and his team helped design the product they 'cloned', therefore had knowledge that anyone else may not have, was not considered by anything or anyone (but Motorola would reconsider this, shortly). Nothing said Peddle could claim the idea and profits from it for himself, on the other hand, nothing said he could not. Motorola claimed 7 employees had left Motorola to make an illegal clone of the 6800. But they only named 4 in the lawsuit. Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill.
Rockwell Automation owned the Allen-Bradley brand and MOS technology was a spin-off of Allen-Bradley. Allen-Bradley sold their interests (and thus liabilities) to MOS employees due to the suit. Note, Rockwell would later create 65xx based hardware. Sales of the 6501 also halted because of a court issued injunction. A judge agreed that Motorola's claims of patent infringement and misappropriation of trade secrets was plausible. Apparently for the 6501's pin layout which replicated the ability to interface with the 6820 PIA chip. Of the trade secrets and twenty-five 6800 related patents Motorola cited, The 6820 PIA interface was the patent Motorola ended up emphasizing. The issue of the 6502's legality was not pursued. Mike James, the team member that left Motorola later than the others to join MOS, had brought 6800 documents to MOS technology. This documentation seemed to be concerning the 6820 PIA interface. Mike James had in fact, worked on the pin layout that had retained compatibility with the 6820 PIA interface. There was actually some dispute as to the confidentially, and therefore trade secretive nature, of this document. At least, this is all what the discovery process had concluded. There was also the complication that Bill Mensch was co-holder of the 6820 PIA Interface patent‡. Mike James, along at least three other teams members, had not been among the MOS employees named in Motorola's suit. The suit took many years and MOS' funds began to run dry (for various other reasons besides the suit). They negotiated a settlement of $200,000 and a cross-licensing agreement† of MOS and Motorola chips. Commodore purchased MOS shortly after. Years later, Jim Bagnall would claim Mike James had stolen and brought a full set of 6800 documents including non-public information with him to MOS. Yet, other team members and MOS employees don't mention Mike James at all.*
The 6501 is just a footnote, the revolution everyone remembers is the 6502. The 6502 fit in it's own socket and arranged the pins differently than a 6800. This was mostly because of all the internal changes but this did have the additional benefit of insulating MOS from being sued by Motorola (Motorola's choice, the pin layout was not considered by any laws). A different socket (in those days) meant it was a different product from the 6800 (along with the other internal differences). Or so it would seem. The 6502 was available for sale at Wescon the same day as the 6501. It shared the ROR bug that would be fixed in later batches. The $20 (Wescon price) 6201 and 6502 weresold separately from the $10 documentation in order to reduce costs of the chip. Later public price for the CPUs would be $25. At Wescon, MOS actually encouraged customers (and non-customers) to make and distribute copies of the documentation (ahh, the good old days before DMCA ruined everything). A 6800 would cost $175 at the time and $300 for the design kit (documentation, militantly guarded intellectual property). This quickly dropped to $69 dollars per chip and $150 for the design kit that hence came with a circuit board kit (so engineers didn't need to etch their own board just to test 6800 code). Motorola would not 'waste' time nor money on anyone but serious (volume) customers (this was standard practice in the industry at the time). Peddle was an effective spokesperson for the 650x and wanted everyone to know the details of how it worked. Engineers and hobbyists especially (these customers didn't order chips in significant volume). At only $25 dollars, engineers and hobbyists would fork over the cash for one of these toys and show off hardware and software to people who did want to buy the chip in volume. He expanded the market and created demand for his chips from a direction the industry had not considered.
The industry and law at the time did not have the totalitarian systems in place to prevent or even discourage a person or team from leaving a company and creating a replica of their product for a competing company (except maybe at RCA). A company could have employment clauses in place for this purpose but management of the Motorola semiconductor division apparently didn't have a strong system of clauses or didn't know the most effective ways to use them. Peddle and his team had very likely not broken any laws*. And, Motorola had most likely walked right into a trap of their own policies by dismissing Peddle's idea. Trade secrets were pretty much not applied to the inner workings of CPUs at the time (they were available at the library and bookstores) and anybody could have done what Peddle did. The fact that Peddle and his team helped design the product they 'cloned', therefore had knowledge that anyone else may not have, was not considered by anything or anyone (but Motorola would reconsider this, shortly). Nothing said Peddle could claim the idea and profits from it for himself, on the other hand, nothing said he could not. Motorola claimed 7 employees had left Motorola to make an illegal clone of the 6800. But they only named 4 in the lawsuit. Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill.
Rockwell Automation owned the Allen-Bradley brand and MOS technology was a spin-off of Allen-Bradley. Allen-Bradley sold their interests (and thus liabilities) to MOS employees due to the suit. Note, Rockwell would later create 65xx based hardware. Sales of the 6501 also halted because of a court issued injunction. A judge agreed that Motorola's claims of patent infringement and misappropriation of trade secrets was plausible. Apparently for the 6501's pin layout which replicated the ability to interface with the 6820 PIA chip. Of the trade secrets and twenty-five 6800 related patents Motorola cited, The 6820 PIA interface was the patent Motorola ended up emphasizing. The issue of the 6502's legality was not pursued. Mike James, the team member that left Motorola later than the others to join MOS, had brought 6800 documents to MOS technology. This documentation seemed to be concerning the 6820 PIA interface. Mike James had in fact, worked on the pin layout that had retained compatibility with the 6820 PIA interface. There was actually some dispute as to the confidentially, and therefore trade secretive nature, of this document. At least, this is all what the discovery process had concluded. There was also the complication that Bill Mensch was co-holder of the 6820 PIA Interface patent‡. Mike James, along at least three other teams members, had not been among the MOS employees named in Motorola's suit. The suit took many years and MOS' funds began to run dry (for various other reasons besides the suit). They negotiated a settlement of $200,000 and a cross-licensing agreement† of MOS and Motorola chips. Commodore purchased MOS shortly after. Years later, Jim Bagnall would claim Mike James had stolen and brought a full set of 6800 documents including non-public information with him to MOS. Yet, other team members and MOS employees don't mention Mike James at all.*
The 6501 is just a footnote, the revolution everyone remembers is the 6502. The 6502 fit in it's own socket and arranged the pins differently than a 6800. This was mostly because of all the internal changes but this did have the additional benefit of insulating MOS from being sued by Motorola (Motorola's choice, the pin layout was not considered by any laws). A different socket (in those days) meant it was a different product from the 6800 (along with the other internal differences). Or so it would seem. The 6502 was available for sale at Wescon the same day as the 6501. It shared the ROR bug that would be fixed in later batches. The $20 (Wescon price) 6201 and 6502 weresold separately from the $10 documentation in order to reduce costs of the chip. Later public price for the CPUs would be $25. At Wescon, MOS actually encouraged customers (and non-customers) to make and distribute copies of the documentation (ahh, the good old days before DMCA ruined everything). A 6800 would cost $175 at the time and $300 for the design kit (documentation, militantly guarded intellectual property). This quickly dropped to $69 dollars per chip and $150 for the design kit that hence came with a circuit board kit (so engineers didn't need to etch their own board just to test 6800 code). Motorola would not 'waste' time nor money on anyone but serious (volume) customers (this was standard practice in the industry at the time). Peddle was an effective spokesperson for the 650x and wanted everyone to know the details of how it worked. Engineers and hobbyists especially (these customers didn't order chips in significant volume). At only $25 dollars, engineers and hobbyists would fork over the cash for one of these toys and show off hardware and software to people who did want to buy the chip in volume. He expanded the market and created demand for his chips from a direction the industry had not considered.
*First-hand accounts of the lawsuit, project progression, organisation of the team, and other details seem to contradict one another on a number of points. I think that there may be a bit of selective memory at play, or just perhaps just fading memories being told the way an audience likes to hear it:) But the technical specs are not disputed.
**projection masking did require physical contact with the projection mask that had similar contamination and defect issues as physical masking on silicon. However, the projection mask was much, much more fault tolerant than a silicon wafer that could be ruined by microscopic defects and damage. MOS was operated much like a small independent company without the same resources as their multi-million dollar competition had. Motorola had Clean Rooms and procedures to minimize risk to a projection mask during manufacture. To bad they weren't using them for projection masking yet. MOS had a spare room and a competent janitor. The projection mask was placed on a very large table and engineers, mostly Bill Mensch, wore clean clothes and socks without holes while they hand crafted the projection mask. Clean socks without holes where especially important because the engineers had to carefully climb on top of the mask to complete the carving. If a toenail scratched the mask, it would produce defective chips. Remember, Mensch only made one mistake on the first batch. 5 years later, MOS would begin construction on a Clean Room but the project ran out of funds before completion. All MOS chips are hand-crafted and not toe-crafted.
***An 8-bit stack is not that bad. As late as 2017, new chip designs were being manufactured that used 6-bit stacks. Apple, Atari, Commodore, Acorn, BBC, Ohio Scientific, Oric, Nintendo, and NEC did quite well offering many systems with 8-bit stacks in their CPUs over many years. For comparison, Coleco. Radio Shack, Sinclair, Sharp, Epson, Cambridge, Amstrad, VTech, Texas Instruments, Bandai, Mattel, Memotech, Timex, made systems with 16-bit stacks in their CPUs. (There's some overlap I didn't list, the 65C816 with a 16-bit stack, for example was used in systems by some of companies on my 8-bit list above.)
†When the lawsuit was settled it left some 3rd parties in a quandary about exactly who owned what concerning the 6501. Many of the patents named in the suit also applied to the 6502. Motorola had listed 25 patents in their suit against the 6501. None were dismissed before the settlement. No ruling was made as to which, if any, of Motorola's patents applied to the 6501 or 6502. It has been speculated that when companies made their own versions of the 6502 that changes were made, in-part, to avoid violating Motorola patents.
‡Some members of team 6502 held patents on design aspects of the 6800. Mensch co-holds the patent of the 6800 CPU itself, the 6820/21 PIA patent, 6850 ACIA patent, and 6860 modem chip patent. He also co-holds the 6502's Decimal Correct Circuitry patent (the feature left out of the NES' Ricoh 2A03 6502 clone)
◊Difficult, but not impossible. First, there are various ways the 6502's two clock outputs can be modified for use with external components. Also important, the 6502 can be made to accept an external signal to modify the internal clock, with limitations. The external clock does not override the internal one. It gets complicated. Some of the 6502 components use combinational logic (clockless logic). Many CPUs may have a bit of combinational logic going on but the 6502 has quite a bit more than most. The 6502's clock is also two-phase and can (should) be synchronized twice per machine cycle. This is how/why the 6502 can fetch the next instruction while processing the current one. This synchronizing function allows for iterations with a clock speed that is slower that the internal clock. This is helpful if the 6502 needs to interact with slower comments, such as an EEPROM during boot. 500KHz is apparently MOS' official minimum spec. Bugs begin occurring under 100kHz because the registers can lose their state. 50KHz has been achieved in real world use. Some features of the 6502 are not available when using a different clock speed.
◊◊Since the suit was filed between the dates of official public sale of the 6501 and 6502, the rumor that the 6502 was a response to the suit must seem plausible to
◊◊◊MOS was shocked to discover, at Wescon, that no one was actually allowed to sell anything at Wescon. Being only momentarily deterred, they rented an addition hotel room to sell out of. Visitors to the MOS booth were given directions to walk to the sales room. In your face, Wescon.
The MDT-650 Microcomputer Development Terminal was a $3950 development system that provided pretty much anything a professional industry development team needed to create 65xx hardware and software for most any hardware or software that would use a 65xx. It was extremely configurable with emulation so a developer could add chips to the wire-wrap board and set parameters to match, for example, an Apple I (when it would exist at some future date), and start creating Apple I software. Equally, a hardware developer could start plugging in wire warp boards an build their own prototype 65xx based computer, arcade board, staging lighting controller, satellite tracking console, medical implant, whathaveyou. The MDT-650 could be used as a full computer. The MDT-650 was Chuck Peddle's design.
The KIM-1 was a minimal development board with keypad and LCD readout created at MOS to offer an easy convenient and inexpensive way for engineers (and perhaps a few students and hobbyists) toplay withlearn about the 65xx architecture. By adding a terminal and cassette drive, these boards could be used as a full computer. This style of board to show off a CPU was common in the industry around this time. However, they were generally not expandable, had no more display or memory than required to demonstration the chip, no storage, and no terminal interface. The KIM-1's minimal expandability was certainly a big part of its higher than expected popularity amongst non-engineers. People at MOS were pleasantly surprised to find that non-engineers turned out to be an equally sized market of customers.
Rockwell AIM-65. Rockwell apparently liked concept of the KIM-1 and made a professional grade development system based on the design. It may not have had all the fancy hardware and emulation of the MDT-650 but it only cost $375. It came loaded with keyboard, punch tape interface, terminal interface, dual cassette, BASIC interpreter, assembler, Pascal, PL/65, and FORTH. It was highly expandable and there was a floppy disk controllers, wire wrap boards, PROM burners, non-volatile storage expansions, a "Visible Memory" card (raster graphics card), and real time music synthesizer with DAC, 4 voices, and wavetable-lookup synthesis. It could do a neat trick of single stepping through machine code. The NMOS 6502 could not do this but Rockwell added some clever external hardware to make it happen. There was also clever cost savings trick to save expense for the customer. The system only had 1K of base RAM, expandable to 4K. How was one to developer for system that used 64K? The AIM-65 had direct control over the cassette drives and would use them instead of RAM. Slow? Hey, we're developing a game here. Send the machine code over to the real system if you just want to play it. Everything was fully documented and source code was included even though the industry was starting to put a stop to such helpful behavior at the time.
The SYM-1 was another development system inspired by the KIM-1. It leaned more to the hardware features the AIM-65 which was clearly software heavy in it's features. In fact, Synertek didn't provide software on cassette or disk. Additional languages, such as BASIC, MAE, and RAE, were available as ROM chips. Note, since these languages were ROM chips, one couldn't _simply_ pirate it over to say a KIM-1 or Apple I. Synertek's "software" was available for many popular computer systems at the time. The SYM-1 had its own clever cost saver for customers. Rather than requiring an expensive terminal or monitor, customers could plug the SYM-1 into a oscilloscope to get 32x16 text display.
The KIM-1 was a minimal development board with keypad and LCD readout created at MOS to offer an easy convenient and inexpensive way for engineers (and perhaps a few students and hobbyists) to
Rockwell AIM-65. Rockwell apparently liked concept of the KIM-1 and made a professional grade development system based on the design. It may not have had all the fancy hardware and emulation of the MDT-650 but it only cost $375. It came loaded with keyboard, punch tape interface, terminal interface, dual cassette, BASIC interpreter, assembler, Pascal, PL/65, and FORTH. It was highly expandable and there was a floppy disk controllers, wire wrap boards, PROM burners, non-volatile storage expansions, a "Visible Memory" card (raster graphics card), and real time music synthesizer with DAC, 4 voices, and wavetable-lookup synthesis. It could do a neat trick of single stepping through machine code. The NMOS 6502 could not do this but Rockwell added some clever external hardware to make it happen. There was also clever cost savings trick to save expense for the customer. The system only had 1K of base RAM, expandable to 4K. How was one to developer for system that used 64K? The AIM-65 had direct control over the cassette drives and would use them instead of RAM. Slow? Hey, we're developing a game here. Send the machine code over to the real system if you just want to play it. Everything was fully documented and source code was included even though the industry was starting to put a stop to such helpful behavior at the time.
The SYM-1 was another development system inspired by the KIM-1. It leaned more to the hardware features the AIM-65 which was clearly software heavy in it's features. In fact, Synertek didn't provide software on cassette or disk. Additional languages, such as BASIC, MAE, and RAE, were available as ROM chips. Note, since these languages were ROM chips, one couldn't _simply_ pirate it over to say a KIM-1 or Apple I. Synertek's "software" was available for many popular computer systems at the time. The SYM-1 had its own clever cost saver for customers. Rather than requiring an expensive terminal or monitor, customers could plug the SYM-1 into a oscilloscope to get 32x16 text display.
PMOS is an early type of integrated circuit design that uses extremely high voltages and is highly tolerant to noise and contaminates in whichever material is used. A wide variety of materials are usable. Aluminium was common, but generally not silicon when PMOS was first used. NMOS and PMOS were simultaneously developed during early electronic computer history. But PMOS 'just worked' before all the difficulties of silicon and NMOS were overcome. PMOS was faster until it was figured out how to make silicon based circuity that was smaller than PMOS. When a PMOS logic gate is in the logical off state, it is not using power. PMOS remains the easier of the two. A PMOS IC can be 'burned' using only chemical etching rather than requiring an ion or optical beam. PMOS ICs can be made in a home garage.
NMOS uses logic circuitry that is always drawing power. Most metals are not suitable for NMOS. Aluminum can be made to work but silicon is generally best for computers. Making NMOS work well is much more complicated than other types of logic circuitry due to the tolerances of materials and tolerances during the manufacturing process. NMOS became commercially competitive with PMOS about 1973.
CMOS (complementary-symmetry metal–oxide–semiconductor) uses symmetrical pairs of NMOS and PMOS circuits and switches between them. CMOS has the advantages of both technologies and loses the disadvantages. When a CMOS logic gate pair is in the logical on state, it is using a lot less power than NMOS. In the off state, it not using power. The only significant power use is when the switch between the two circuit sides happens. Most circuits spend most of their time not switching. Overall CMOS consumes less power and produces less heat. Circuitry can be more dense. Even though is uses silicon more efficiently, CMOS costs more to manufacture. CMOS greatly increases the complexity of reverse engineering. For decades, CMOS was slower than NMOS but is now considerably faster. CMOS can be analog or a mix of digital and analog, but analog applications are limited due to practicality. CMOS currently makes up more than 99% of all chip designs on the market.
HMOS is NMOS where all internal circuitry uses the same voltage. This is called "depletion-load" design in both types. MOS's original 6501 and 6502 are not HMOS, they used a single external voltage but created multiple voltages internally (partial depletion-load).
NMOS uses logic circuitry that is always drawing power. Most metals are not suitable for NMOS. Aluminum can be made to work but silicon is generally best for computers. Making NMOS work well is much more complicated than other types of logic circuitry due to the tolerances of materials and tolerances during the manufacturing process. NMOS became commercially competitive with PMOS about 1973.
CMOS (complementary-symmetry metal–oxide–semiconductor) uses symmetrical pairs of NMOS and PMOS circuits and switches between them. CMOS has the advantages of both technologies and loses the disadvantages. When a CMOS logic gate pair is in the logical on state, it is using a lot less power than NMOS. In the off state, it not using power. The only significant power use is when the switch between the two circuit sides happens. Most circuits spend most of their time not switching. Overall CMOS consumes less power and produces less heat. Circuitry can be more dense. Even though is uses silicon more efficiently, CMOS costs more to manufacture. CMOS greatly increases the complexity of reverse engineering. For decades, CMOS was slower than NMOS but is now considerably faster. CMOS can be analog or a mix of digital and analog, but analog applications are limited due to practicality. CMOS currently makes up more than 99% of all chip designs on the market.
HMOS is NMOS where all internal circuitry uses the same voltage. This is called "depletion-load" design in both types. MOS's original 6501 and 6502 are not HMOS, they used a single external voltage but created multiple voltages internally (partial depletion-load).
65C02 mainly, is a CMOS version of the NMOS 6502. It uses 20mW when running at 1MHz. The NMOS 6502 at 1MHz used 450mW. It also has some bug/quirk fixes and 13 additional instructions (69 total). It has 212 unique opcodes with the remaining 44 opcodes hard coded as NOP (manufactures can have variants with up to 44 custom opcodes). It remains an 8-bit CPU. Originally available at 1MHz, 2MHz, and 4MHz speeds, later versions achieved 14MHz in real world applications. Later variants can be adjusted by external hardware to any needed frequency between 0MHz and 14MHz. Program counter and address bus were increased to 16-bit. The Flags were improved and renamed as the "Status Register". Zero Page (256 bytes of optional general registers in RAM) access speed was increased. The 256 byte stack was fixed to RAM page one. It has a variable-length instruction set with 2 and 3 byte instructions added. It has 16 addressing modes. Some variants can be run under 50MHz or even stopped with no loss of data. There was finally a simple way for hardware to share the bus with a 6502 without adding a bunch more hardware (expense). WAI and STP operations can be used to maintain the CPU's state while using minimal power and the chip can maintain this state while other hardware controls the system bus. FPGA implementations of the 65C02 can run at 200MHz. Assembly language programs can be written for the 65C02 that are up to 15% faster than an NMOS 6502 running at the same clock speed. To correct the index cross page boundaries bug, and the extra read for R-M-W instructions, CMOS variants read the correct value twice (presumably to use up a clock cycle to maintain compatibility) and the extra reads will not trigger hardware. This introduced a new error. Reading on an even page boundary (xx00) can confuse hardware if there is an IRQ event at the time.
The 8502 is an HMOS-II version of the 6502. It used less power, produced less heat, and was physically smaller. Being smaller, it was cheaper (read A Condensed History above to better understand why).
[wip]
MOS 4510
MELPS M50740 (600 variants are not all listed)
Ricoh 5A22
MOS 6501 A, 6501 B, 6501 C
MOS 6502 A, 6502 B, 6502 C
MOS 6503
MOS 6504
MOS 6505
MOS 6507
MOS 6508
MOS 6509
MOS 6510, 6510T
MOS 6512
MOS 6513
MOS 6514
MOS 6515
? 65802
? 65816
WDC 65C02
WDC 65C134
WDC 65C265
WDC 65C802
WDC 65C816
MOS 65CE02
MOS 7501
MOS 8500
MOS 8501
MOS 8502
Hudson Soft HuC6280
Nintendo SA-1 (65C816 based)
Ricoh RP2A03
Ricoh RP2A07
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The first 6502 CPU video game was released in 1977.